Power consumption by electronic devices is an increasingly important factor in the design of electronic devices. From an environmental perspective, the energy consumption of electronic devices occupies a sizable percentage of total energy usage due to large corporate data centers and the ubiquity of personal computing devices. Environmental concerns thus motivate efforts to reduce the power consumed by electronic devices to help conserve the earth's resources. From a financial perspective, less power consumption translates to lower energy bills for both corporations and individuals.
Furthermore, from a convenience perspective, many personal electronic devices are portable and therefore powered by batteries. The less energy that is consumed by a portable battery-powered electronic device, the longer the portable device can operate without recharging the battery. Lower energy consumption also enables the use of smaller batteries and the adoption of thinner form factors, which means electronic devices can be made more portable or versatile. Thus, the popularity of portable electronic devices also motivates efforts to reduce the power consumption of electronic devices.
An electronic device consumes power if the device is coupled to a power source and is turned on. This is true for the entire electronic device, but it is also true for individual parts of the electronic device. Hence, power consumption can be reduced if parts of an electronic device are powered down, even while other parts remain powered up. Entire discrete components of an electronic device, such as a whole integrated circuit (IC) chip or a display screen, may be powered down. Alternatively, selected parts of a discrete component may likewise be powered down. For example, a distinct processing entity or a circuit block of an integrated circuit chip, such as a core thereof, may be selectively powered down for some period of time to reduce energy consumption.
A portion of an integrated circuit, such as a core, can therefore be powered down to reduce power consumption, which conserves energy and extends the battery life of portable electronic devices. A core can be powered down by decoupling the core from a power source or by turning the power source off. This causes the core to cease using energy. Additionally, a core can be powered down by lowering a voltage supplied to the core or lowering a frequency at which the core operates. Lowering a voltage or a frequency of operation can therefore reduce the energy used by the core. Thus, as used herein, the term “powering down” can include ceasing energy usage or reducing energy usage.
Given these factors, two conventional approaches to reducing energy usage have been developed for integrated circuits. One approach to reducing the energy usage of a block of an integrated circuit is to supply a lower voltage level to the block. This approach is called dynamic voltage scaling (DVS). With DVS, power usage by a block can be managed by lowering a supply voltage during times of reduced circuitry utilization and then raising the supply voltage to meet higher utilization demands. Another approach to reducing the energy usage of a block of an integrated circuit entails lowering a frequency of a clock signal supplied to the block. This approach is called dynamic frequency scaling (DFS). Similar to DVS, power usage by a block can be managed with DFS by reducing a clock frequency during times of reduced circuitry utilization and then raising the clock frequency to meet higher utilization demands.
DVS and DFS can also be used together to implement dynamic voltage and frequency scaling (DVFS). With DVFS, a supply voltage or a clock frequency, including possibly both, are adjusted to change a current power consumption level of a block. Thus, DVS, DFS, or DVFS can be employed as a power management technique to reduce the power consumption of electronic devices.
Unfortunately, implementing DVS or DFS individually or in a combined manner as DVFS is challenging. For example, implementing conventional approaches to voltage or frequency scaling can adversely impact the performance of an integrated circuit, especially during phases in which the voltage or frequency is actually being changed. Typically, processing is halted during voltage or frequency transitional phases. Consequently, overall data throughput is slowed as a result of efforts to reduce power consumption. Furthermore, conventional approaches to voltage scaling have resulted in complicated chip layouts with substantial areas of the chip devoted to different power rails that are held at different voltages at different times. These issues have hindered the deployment of DVS, DFS, and DVFS and have therefore prevented the attainment of the full power-conserving potential of voltage and frequency scaling.